Paul A. Clayton
  • Member for 9 years, 2 months
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Can CPU's 'shortcut' adding 0, multiplying by 1, and multiplying by 0?
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In general, processors do not detect and special case identity elements (zero addends, zero shifts, one multiplicants, one divisors) or zero multiplicands. Addition is typically extremely ...

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How can i compute tag-index-displacement bits of an address if cache size is not a power of two?
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The straightforward manner of indexing and tagging a cache is for the index to be the address (in blocks, i.e., removing the block offset) modulo the way size (in blocks) and for the tag to be the ...

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What are some "easy" unreasonable implications of O(1) time memory access?
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The easiest unreasonable implication is that such ignores the impact of temporal and spatial locality of reference in conventional systems. Processor caches cause accesses to other addresses within a ...

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use of unconditional transfer of control instruction
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As David Richerby's answer notes, the most common use is for implementing if-then-else, where the unconditional jump hops over the else code. A related use is when the compiler knows conditional code ...

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Are hardware specs relevant in software performance comparisons?
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Performance comparisons are not hardware agnostic because performance does not scale proportionately for all applications across all computers. Even if the relative performance of a particular ...

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Why do we have to trade abstraction for speed?
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By its nature abstraction reduces the communcation of information, both to the programmer and to the lower layers of the system (the compiler, libraries, and runtime system). In favor of abstraction, ...

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What happens if the associativity level is greater than the cache size?
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Since the associativity is equal to the number of cache blocks in a set, in a traditional cache design there is no sensible interpretation of having associativity greater than capacity; a set cannot ...

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speed, cost and capacity tradoff
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Increasing the speed of memory typically involves increasing the size of the bit cell. For example increasing the capacitor size in a DRAM (which using one transistor and one capacitor to store a bit) ...

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Where do these DRAM row/column calculations come from?
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The first value describing the DRAM is the number of data-interface-sized "chunks" it contains and the second value is the width of the data interface in bits, i.e., bits per "chunk". A 16x1 DRAM ...

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In a 32-bit floating number with normalized mantissa and excess-64 exponent base 16, the number $16^{-65}$ denotes
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The format you are using is not IEEE-754 but an IBM FP format. The mantissa is fractional, so the binary representation 0001_0000_0000_0000_0000_0000 means 0.1 (base 16). With a zero value in the ...

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Dynamic selection of cache replacement policy
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"Adaptive Insertion Policies for High Performance Caching" (PDF) uses set dueling (where a portion of sets are assigned to different policies for tracking) to select insertion as LRU (next victim). ...

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Can each VLIW sub-instruction execute any instruction?
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As TEMLIB's answer indicates, VLIWs generally limit what operations can be encoded into each slot of the instruction word. The primary constraint is actually structural hazards. The area and power ...

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Is automatic multicore support at the hardware or compiler level possible?
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Automatic parallelization of software (at the source code level down to the hardware level) has been actively researched and in some areas has achieved significant speed-ups. This effort can roughly ...

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Why would anyone want CISC?
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There are many reasons one would choose to implement a CISC. The most prominent reason is for binary compatibility with an existing CISC instruction set. While software binary translation technology ...

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On a semiconductor chip, what state (on/off or read/write) corresponds to conducting or insulating behavior?
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In general it is conventional to use high voltage for true/one and low voltage for false/zero. In fact, a notation with the signal name overscored ($\overline{SIGNAL}$) is used to indicate active-low (...

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