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Mar 24 at 7:57 comment added gnasher729 Processor designers don’t care what textbooks say.
Jan 20, 2018 at 21:21 answer added gnasher729 timeline score: 0
Jun 20, 2017 at 19:22 answer added AProgrammer timeline score: 2
Jun 20, 2017 at 14:45 comment added Raphael @DavidRicherby I can't claim to remember with any accuracy, either. We should probably shut up and let the experts deal with this. :'D
Jun 20, 2017 at 13:37 comment added David Richerby @Raphael I'm gonna plead forgetfulness based on the time since I last studied computer architecture!
Jun 20, 2017 at 13:02 comment added Raphael @DavidRicherby True. I mixed up pipeline and "only some instructions access memory". Sure, we can slow down everything to memory-access speed. IIRC this is not done, though?
Jun 20, 2017 at 8:26 comment added David Richerby @Raphael A pipeline still makes sense even if each instruction takes the same amount of time to execute, since there are multiple stages to execution.
Jun 19, 2017 at 21:46 comment added Raphael Weird. Afaik, MIPS counts as RISC and is has a pipeline and everything. Anyway, please include the reference into your question. Take care to use scientific standards for citations!
Jun 19, 2017 at 21:43 answer added Grabul timeline score: 0
Jun 19, 2017 at 21:00 comment added Harry Boulton Those exact words are from my courses text book, but Stanford university: "RISC processors only use simple instructions that can be executed within one clock cycle" cs.stanford.edu/people/eroberts/courses/soco/projects/risc/…
Jun 19, 2017 at 20:52 comment added Raphael "my understanding is that all instructions in a RISC architecture should execute in roughtly the same" -- why? Can you cite the material that makes you think that?
Jun 19, 2017 at 20:51 history edited Raphael
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Jun 19, 2017 at 20:42 review First posts
Jun 20, 2017 at 8:26
Jun 19, 2017 at 20:38 history asked Harry Boulton CC BY-SA 3.0