Do CPUs have big circuits such as asynchronous multipliers or BCD to binary converters?
An asynchronous multiplier is much bigger than an adder. It's about 18*n^2 NOR gates where n is the number of bits. An adder is about 15*n NOR gates. But for a 32-bits multiplication, a multiplier with successive additions will need 32 clock cycles, while an asynchronous mutliplier only 1. I think it's a big performance gain.
The same is for BCD to binary converter.
Last time I checked (more than 15 years ago), Wallace trees (and variants such as Dadda trees) were still the state of the art ($O(N^2)$ number of gates, but $O(\log N)$ latency; if you are naive in the way you do the additions, the latency may be $O(N)$).
Note that multipliers may be pipelined so you can still achieve a throughput of one multiplication per cycle but with a latency of more than one cycle if the latency of the multiplier is too big for your target clock rate.
Of course, it depends on the type of CPU. Primitive 8 bits CPUs had no multiplier (until the MC6809 which had a 8bits x 8bits multiplier :-).
Modern CPUs have both fast integer and floating point multipliers. The FP multipliers are replicated for "multimedia" SIMD instructions and there are also plenty of fast multipliers in the GPU.
Depending on the transistor budget, one may make a pipelined 1 cycle throughput double precision (53x53 bits) multiplier, or make only single precision 1 cycle and 2 or 3 cycles for double precision. Some GPUs still have this sorts of limitations.
In a modern FPU, the multiplier is often coupled with an adder and the mul/add operation can be done in 3/4 cycles, pipelined (so that a result can be obtained every cycle, as long as there is no data dependency). The core multiplication part lasts 1 cycle, while the other cycles are used for data algnment, conversion, rounding... There are many tricks for implementing multipliers using fewer gates than cascaded adders. Look for Booth encoding, Wallace trees... but it is more about EE than CS.
About decimal
x86 have some decimal parts, now obsoleted but still present. There are the AAA, AAS, AAD, AAM instructions, unavailable in 64bits mode, wich are helpers for BCD arithmetics. The FPU x87 instruction set has instructions to read/write decimal numbers from memory and convert on the fly to/from binary (internal registers are binary).
Some high end CPUs, notably IBM servers/mainframes, feature decimal FPUs specifically for financial operations with are officially based on decimal rounding and cannot be easily implemented exactly on binary FPUs.
I thought a 7/3 adder was 18 gates and you'd need less than 1000 of those for a full 64x64 multiplier. No big deal. And about 4 n^2.
There is absolutely no demand for BCD converters in hardware. Nothing that can't be done quicker with a lookup table.
