Is Everything a Hardware Interrupt?

Question

Just need a little help understanding hardware interrupts.

As I understand (feel free to correct) a hardware interrupts occurs when hardware wants attention of the computer. In basic terms the hardware sends a message down the interrupt line which is then controlled by the PIC. The CPU receives the interrupt and carries out the instruction once it has completed the current one it is on.

Every time I've seen examples of interrupts they have been 'printer running out of paper', 'network adapter receiving data packet' etc. My question is, how is the process of the hardware interrupt any different from pressing a key on a keyboard or moving a mouse? Each of these actions requires attention from the CPU but as I understand they are never used as examples of interrupts. Are they interrupts? Does everything I do with an input device cause an interrupt?

Any clarification would be much appreciated.

Answer 1

In general, no, on modern platforms, not everything is a hardware interrupt -- though you could imagine a platform where it is.

On some platforms, hardware interrupts are used for all input events (including, yes, pressing a key on a keyboard or moving a mouse).

However, interrupts come with some performance implications. Therefore, in modern platforms, we often use a combination of interrupts and other I/O mechanisms. We might use interrupts for some input devices, but other input devices might use memory-mapped I/O. For instance, your Ethernet card might use memory-mapped I/O, to write incoming packets into a region of memory dedicated for this use. Memory-mapped I/O can be combined with interrupts or with polling.

You can find more on interrupts, polling, memory-mapped I/O, DMA, and related topics in a good operating systems textbook.

Answer 2

Not everything is a hardware interrupt. Hardware interrupts are mostly used to gather input from IO devices. Today, it is rather complex and quite different from how it used to work with the old 8259 PIC. Today, there's a combination of IO APIC which serves the whole CPU and local APIC which serves a specific core of the CPU.

The IO APIC is becoming more and more obsolete with the MSI/MSI-X capability of PCI devices. PCI devices are MMIO meaning that you write to certain (uncached) part of RAM and it sends the data to the PCI devices instead. I don't know exactly how it is implemented in hardware itself. I would guess that there is a separate part in the CPU which is configured by the PCI devices themselves. For example, when you plug a PCI device, it would send signals to the CPU. Again, I don't know how that works exactly. What I know is that the configuration space of a PCI device can change position. For example, a BAR can point to different addresses depending on the device and its version.

Most chips today are PCI-express and they have the mandatory MSI-X capability. They thus bypass the IO APIC and send some kind of inter-processor interrupt to the CPU. It thus makes the IO APIC more and more obsolete because everything is PCI today.

For x86, you could think of the AHCI which drives SATA hard-drives, the xHCI which drives USB devices, network cards which are PCI or graphics cards which are also PCI.

Answer 3

I think there is quite a lot lacking from the above answers.

Let’s first think about what an interrupt provides. An interrupt is how we accomplish preemption in a computer system. That is, stopping program execution in arbitrary positions in their code. All preemption in a computer system is accomplished via interrupts. Many software frameworks and operating systems have features that feel & look like preemption but without an interrupt it has not actually preempted a processor core.

There are a few different kinds of interrupts, maybe more than listed

Line Interrupts - A physical wire/pin on the CPU. Trigger types: (Edge Triggered/Level Triggered)

Messaged Interrupts - There aren’t enough pins on the CPU to support enough interrupts in modern computers. Modern CPUs such as Intel/AMD with many cores have a network inside of the CPU between cores, cache, memory & I/O. Messaged interrupts are effectively a packet in the CPU core/mesh network. It is a hw implementation.

NMI - Non-Maskable interrupt. Interrupt that cannot be ignored, most commonly used to crash/shut down a system after an uncorrectable error etc.

Interrupts controllers often supports interrupt priority. Some interrupt controllers support interrupt nesting. (Interrupting an interrupt)

Most people talk about I/O as being the most common source of interrupts. There are a few other interrupt sources of interest.

Timers - Processor can set a hw timer & receive an interrupt when the timer expires.

MMU - memory management unit sends interrupts on TLB exceptions. Page faults etc.

Errors - Many things can generate interrupts when a correctable or uncorrectable error occurs. (DRAM, PCIe devices etc). Processor Exceptions such as overflows, zero division, segment errors, protection faults etc.

CPU Cores - Many platforms support CPU cores sending interrupts to other CPU cores. A common thing in some OS schedulers for task migrations etc.