Sorry for the late answer. The Memory Management Unit doesn't hold page tables. It holds a TLB (Translation Lookaside Buffer). The TLB holds translations of virtual addresses to physical addresses that were done recently. It isn't managed by the OS (like any cache) but can be flushed by loading the CR3 register on x86.
I don't know if you are familiar with x86. The x86 computers have timers that throw interrupts. When a timer interrupt happens, the OS will give a time slice to another process and reschedule the timer. To change process, the OS will change the CR3 register to point to a new PML4 (first level of page table on x86-64). When it does that, the TLB is flushed by the processor. It thus allows to remain consistent.
Every core of the processor runs only one process/thread and, yes, every core has its own CR3 register. When the context switch occurs, the new process has its own page tables and they are swapped simply by reloading CR3. The page tables are stored in RAM and managed by the OS.
Hope this clears any misconceptions you have.