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Results tagged with mips
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user 83222
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vote
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answer
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Why does this branch data hazard happen during the instruction decode stage?
Suppose I have the following MIPS code on a CPU with forwarding enabled:
L1: LW R2 0(R1)
ADDI R2 R2 2
SW R2 0(R1)
ADDI R1 R1 8
SUB R4 R1 R3
BNEZ R4 …
- 175
2
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Accepted
Why does this branch data hazard happen during the instruction decode stage?
In the MIPS pipeline, for branches and jumps, all of the arithmetic is done in the instruction decode portion of the pipeline. … See this MIPS handbook pg. 9, or this handy UCSD ppt. explaining the rationale for this design choice on slide 14. …
- 175