Direct map cache uses a valid bit to effectively know if any data is present to a specific cache-slot (aka line/index). If this is the only use of this bit, then I believe, once a line has v-bit set, it won't be unset until power off.

In addition, I wonder why similar optimization has not been done for associative (full or k-way) cache. Only reason I could imagine is that since for every read/write, a cache-slot will be filled, the cache will be filled pretty soon; and the probability of a slot being empty is zero in no time.

Any feedback will be much appreciated.

  • 1
    $\begingroup$ There is some form of validity bit for every line in every type of cache. Otherwise, at power-up, tags will be random and there is the risk of a false hit. $\endgroup$ Jun 27, 2019 at 15:23
  • $\begingroup$ @ Alan Merigot - I thought CPU caches are volatile! If so, why would tags be random at power-up $\endgroup$
    – KGhatak
    Jun 27, 2019 at 18:23
  • 1
    $\begingroup$ They are volatile. Their content is lost at power down. At power up, the content of a flip-flop/memory cell is undetermined for electronic reasons. So, it is part of the boot process to invalidate all cache blocks. $\endgroup$ Jun 27, 2019 at 19:42


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Browse other questions tagged or ask your own question.