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Questions tagged [cpu-cache]

A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.

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Inverting position of MMU and cache inside a computer

I was thinking about a topic in my actual course and a question came to my mind. What would happen if, at the hardware level, the position of the MMU and the cache were reversed inside a computer? ...
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MIPS: How can the least 2 significant bits of a 32-bit address specify a byte?

I was reading Computer Architecture Organization and Design by David A. Patterson and John L. Hennessy. Specifically, I was reading chapter 5, section 5.3, Basics of Caches. I read the following ...
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Measuring Cache Access Time

I want to make a simple C program in order to measure L1, L2 and L3 latencies of my CPU. I know some info about them: ...
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What is dynamic biased cache replacement policy?

The Arm documentation for Cortex-A76 (Raspberry Pi 5) says the L2 cache replacement policy is "dynamic biased". But what is it? More precisely: How does it works? Why not using pseudo-LRU, ...
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Performance considerations of index maps for rearranging a vector

Imagine two vectors $V=[v_1, v_2, \ldots, v_n]$, $S=[s_1, s_2, \ldots, s_n]$ where $S$ is a rearrangement of $V$ based on some relation $\leq$. Imagine that, instead of computing $S$ using as input $V$...
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Cache Miss in First Private Cache but Hit in Shared LEvel 2 Cache: Does it Result in a Penalty?

In the context of Shared Memory Multiprocessor (SMP) systems with different cache levels, if a cache miss occurs in the first private cache but is followed by a hit in the second shared cache, would ...
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How to calculate memory bandwidth?

I'm studying for final and currently stuck in the question below. You have an embedded processor. It has its L1 instruction and data cache. No L2 or last level cache are available. Consider the ...
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Understanding atomic requests/transactions in a snooping coherence protocol

I've been reading the book "A Primer on Memory Consistency and Cache Coherency", and it contains the following paragraph: The Atomic Requests property states that a coherence request is ...
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Is loading from L2 or L3 of multi level cache direct or require a transfer to L1

(This is mainly about reads, and commercial products not hypothetical machines.) When loading a CPU register with data contained in L2 or L3 of a multi-level cache. Can the data that is in L2 or L3 ...
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Associative memory addressing

I would like to understand better how associative memory works.In associative memory we have the tag and the actual data being stored.The tag describes where the data came from but what does this mean ...
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I'm completely stumped by these questions for a Computer Organization assignment

My Professor for my Computer Organization class gave us a few questions about caches on an assignment. I'm completely stumped by most of them. I've watched a few videos on caches on YouTube by ...
Kseniya Kolokolkina's user avatar
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How is the memory address structured when the number of blocks per cache set is not a power of 2?

When it comes to defining the memory address structure given the RAM size, cache size, and other parameters such as the cache block size..., we can have the following generalization: $$Address = TAG|...
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Adding two 2D matrices together: row by row vs column by column

When adding two 2D matrices of the same size (in row major format), in sequential code with no vector operations, is it faster to add them column by column or row by row? At first I thought it would ...
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Can compilers improve performance in real workloads by inserting prefetches in their output?

Prefetching is a task that the compiler feels like it should be suited for. Prefetching requires knowing in advance what data the program is about to load, and the compiler has a ton of information at ...
Narrateur du chaos's user avatar
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Help with a question on write-through and no-write allocate in caches

I am struggling with this question as I am not sure whether the answer that has been provided is correct or not. The image should be sufficient to tell the question. The attached image is of the ...
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Memory Hierarchy Mappings to real world

This article from IBM (link) talks about Memory hierarchy in its actual hardware parts. NUMA While operating systems present memory to the running applications as a unified space, modern large ...
isomorphik's user avatar
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Page/Frame VS Block

I am bit confused on these terminologies. While studying Paging of Operating System we study about Page and Frame. Size of one Frame of Main Memory = Size of one Page of a Process While studying ...
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compute cache miss rate by given code

I have been trying to solve questions like this before but I have stumbled in difficulty to track the the space of the cache. so there is an example of a question like this: Given the code: ...
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Are really only ~1% of the physical CPU space used for computing

In a Talk by Herb Sutter C++ and Beyond 2012: Herb Sutter - atomic Weapons 1 of 2 at 46:30 the point is made that only around 15% of the physical space (or the transistors) on a CPU do actual ...
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Direct-Mapped cache for Multicore Processor using MSI Protocol

I am reading a case study for Computer architecture, A Quantitative Approach 5th Edition. For reference, I am looking at the case study #1 in Chapter 5 and none of it is making any sense. It says: ...
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CPU cache sets and address bits

I have some questions about CPU caches I would like some clarification on. Assume that I have a 128 KB cache with a block size of 64. It is 4-way associative. How many sets does the cache have? How ...
Bradley Lund's user avatar
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How to decide row / column strides for a loop over a matrix get these cache hit rates?

Given CPU with: L1 cache: 4-ways, block size = 32 bytes , cache size = 64KB , LRU (Cache replacement policy). L2 cache: 2-ways, block size = 32 bytes , cache size = 512KB , LRU (Cache replacement ...
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Von Neumann mixed with Havard in modern CPU?

Modern CPUs (for a very wider range of "modern") use separate data- and instruction-caches. So at the core they (probably) have separate busses for data and instructions. Does that make the &...
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Performance of CPU with two caches

I was very confused how to solve the problem when there are two levels of cache, My doubt is how does we quantify the performance when there are two caches. Consider a problem like this Cache L1 ...
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Are sample memory access traces/dumps available, and where?

I am looking for a realistic physical memory access trace/dump of significant, but not insane, length (on the order of 1M accesses) for the purpose of cache simulation. Preferably for a 16-bit or 32-...
DYZ's user avatar
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Where does tag directory is stored

I am studying direct mapping in cache. I understood the concepts like dividing into blocks and lines , tag directory etc. When solving numerical problems of finding main memory size or tag directory ...
Brijesh joshi's user avatar
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8085 microprocessor connection of CPU data bus with RAM data bus

What would happen if the CPU data-bus bit 2 is connected to the RAM data-bit 5 and CPU data-bus bit 5 is connected to RAM data bit 2? Assume the rest of the connections are all right – explain.
Yukti Kumari's user avatar
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1 answer
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How can an instruction be fetched every cycle?

From what I understand, in a pipelined CPU, every stage takes 1 cycle. But instructions are fetched from memory which takes up to ~150 cycles. The CPU fetches most instructions from the L1-cache, but ...
seb's user avatar
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Confusion regarding calculation of estimated memory access time in a system containing only a cache and main memory for simplicity

Let us consider a system having cache and main memory. Now suppose we are asked to find the average memory access time. Let $h$ be the hit ratio for the cache, $t_c$ be the cache access time, $t_m$ be ...
Abhishek Ghosh's user avatar
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How does software prefetching work with in order processors?

From prof. Onut Mutlu's slides on prefetching, this example has been shown as software prefetching: ...
Rufat Imanov's user avatar
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How to determine offset bits when addressing CPU cache?

I know that the offset is based off of the line size for a cache. I have seen the example: "32-btye line size would use the last 5-bits (i.e. $2^5$) off the address as the offset into the line&...
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Cache memory temporal locality and spatial locality principles

How does cache memory take advantage of both temporal locality and spatial locality principles?
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How could one construct a TLB so that not all the bits of the presented address need match to result in a hit?

I was wondering besides the typical matching of all bits in the presented address to the resulting page, is there another way of doing so? what are the benefits/ cons and how would one go about doing ...
I'veGotSomeQuestions's user avatar
2 votes
1 answer
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Would increasing system memory speed reduce a Von Neumann Architecture bottleneck?

A Von Neumann Architecture bottleneck is a limit on the amount of data a computer can process due to limited bandwidth between the CPU and RAM. Possible mitigations to the problem according to ...
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Formula to see where a memory address can be depicted in cache?

I've been trying to find a formula that helps us identify where an address can be depicted in cache. I remember my professor talking about some kind of division but I can't find it in my textbook nor ...
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Query Regarding Direct cache mapping [closed]

Thank you for looking into this, I have a problem regarding direct cache mapping, My problem really though is with the question formation itself and the problem I am about to present seems to have ...
Pawan Nirpal's user avatar
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Cache read controller

Does the cpu interface with a memory controller to read the cache? What happens when data is not in the cache, a cache miss, does it automatically fetch the data?
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Calculate the effective access time

This question seems to be causing a lot of debate and I'm wondering whether my working is correct. A computer with a single cache (access time 20ns) and main memory (access time 500ns) also uses the ...
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7 answers
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What is a cache write miss?

I'm reading Computer Organization and Design MIPS Edition 5th Edition The Hardware/Software Interface on how memory cache works. I came across the following paragraph on page 393; The other key ...
Jamāl's user avatar
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What does "associative" exactly mean in "n-way set-associative cache"?

I'm trying to grasp what does associative actually mean in n-way set-associative cache. I understand n-way set-associative cache as a concept; n is the degree of ...
adder's user avatar
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I'm to calculate the tag, index and offset for a given setup

Total Memory size = 65,536 bytes Number of cache blocks = 32 cache blocks Cache size = total 512 bytes So using this info provided I cannot figure out how to calculate the cache block number. I know ...
Eehit Ray's user avatar
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Cache Miss and Processor Speed

today in my class my professor mentioned that Cache misses becomes more expensive as the speed of the processor increases But he didn't explain the reason. I ...
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Find main memory location in cache(direct mapping)

Consider main memory of the size 64 kB with each word being 8 bits(one byte) only and a direct mapping Cache memory of size 4 kB also having data word size 8 bits. Find the following : Find the size ...
anuj goyal's user avatar
1 vote
1 answer
190 views

How does the cache / memory know where to return results of read requests to?

The pipeline of a modern processor has many stages that may issue read requests to main memory, e.g. in fetching the next command or loading some memory location into a register. How is the result of ...
Martin Berger's user avatar
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Computing average access time

A computer has a cache memory and a main memory with the following features: - Memory cache access time: 4 ns - Main memory access time: 80 ns - The time ...
jin kaido's user avatar
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Virtual Memory vs Cache for block identification

Both are based on the principle of locality. Then why virtual memory uses table lookup while cache memory uses associative memory for block identification?
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Cache write misses

I've been using Intel Pin tool to perform analysis of cache miss rates of a parallel application in multi-level caches, using one of the examples allcache.cpp, the results differentiate load and write ...
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How does a cache handle overwriting between 2 addresses in the same block?

Consider a byte-addressable cache with block size 16 bytes, bytes 0-15 form one block. First I write an int(let's say 7) to address 0, so now bytes 0-3 contain the int 7. Now if I try to write another ...
hey dude's user avatar
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5k views

Average access time in two level cache system

In a two-level cache system, the level one cache has a hit time of 1 ns (inside the CPU), hit rate of 90%, and a miss penalty of 20 ns. The level two cache has a hit rate of 95% and a miss penalty of ...
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Size of the data bus connecting CPU cache and RAM?

I'm reading about CPU caches and I read that typically, cache line sizes start from 32 bytes. Since memory is slower than CPU caches therefore data is frequently loaded from the RAM into the cache and ...
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