Questions tagged [cpu-cache]
A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.
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Cache/RAM transfer time
I'm studying computer memory and I can't understand the following thing.
In a computer architecture is correct to assume that the access time to a word is equal to the transfer time of that word? I'm ...
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1answer
35 views
How does software prefetching work with in order processors?
From prof. Onut Mutlu's slides on prefetching, this example has been shown as software prefetching:
...
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How does changing cache size and/or block size affect the hit rate of the for loops in the following code?
I am working on practice problems to study for an upcoming exam. I am given the following piece of code:
...
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1answer
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How to determine offset bits when addressing CPU cache?
I know that the offset is based off of the line size for a cache. I have seen the example: "32-btye line size would use the last 5-bits (i.e. 25) off the address as the offset into the line" ...
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Cache memory temporal locality and spatial locality principles
How does cache memory take advantage of both temporal locality and spatial locality principles?
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How could one construct a TLB so that not all the bits of the presented address need match to result in a hit?
I was wondering besides the typical matching of all bits in the presented address to the resulting page, is there another way of doing so? what are the benefits/ cons and how would one go about doing ...
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1answer
64 views
Would increasing system memory speed reduce a Von Neumann Architecture bottleneck?
A Von Neumann Architecture bottleneck is a limit on the amount of data a computer can process due to limited bandwidth between the CPU and RAM. Possible mitigations to the problem according to ...
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1answer
154 views
Formula to see where a memory address can be depicted in cache?
I've been trying to find a formula that helps us identify where an address can be depicted in cache. I remember my professor talking about some kind of division but I can't find it in my textbook nor ...
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1answer
65 views
Query Regarding Direct cache mapping [closed]
Thank you for looking into this, I have a problem regarding direct cache mapping, My problem really though is with the question formation itself and the problem I am about to present seems to have ...
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1answer
35 views
Cache read controller
Does the cpu interface with a memory controller to read the cache? What happens when data is not in the cache, a cache miss, does it automatically fetch the data?
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Calculate the effective access time
This question seems to be causing a lot of debate and I'm wondering whether my working is correct.
A computer with a single cache (access time 20ns) and main memory (access
time 500ns) also uses the ...
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2answers
756 views
What is a cache write miss?
I'm reading Computer Organization and Design MIPS Edition 5th Edition The Hardware/Software Interface on how memory cache works. I came across the following paragraph on page 393;
The other key ...
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Double Write After Write Dependency in out-of-order/in-order executions
What is going to happen when we have a WAW(write after write) dependency which consists of two consecutive WRITE instructions into the same register.
We know we can solve a simple WAW dependency by ...
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Cache Direct Map access confusion
Ok, I've found a good example
But it doesn't really answer my question.
Simple Example
We have a 8 two-word blocks. So we have an offset of 1 bit.
Say we have two references 33 and 32.
...
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Functionning of the eviction set for Prime and Probe
I have to write a report about Prime and Probe, more specifically about its eviction set method, and there are two notions that remain blurry for me :
To find the set, we use huge pages like it's ...
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0answers
21 views
Help understanding main memory to cache block mapping
I'm currently self-learning on the cache memory and have come
across a method on how to find out which cache block a memory address will be
mapped to:
...
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1answer
98 views
What does “associative” exactly mean in “n-way set-associative cache”?
I'm trying to grasp what does associative actually mean in n-way set-associative cache. I understand n-way set-associative cache as a concept; n is the degree of ...
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Hardware implementation of direct mapped , set associative mapped and fully associative cache
I have consulted many textbooks (Morris Mano, H.P Hayes, Hamacher, William Stallings) but could not find a standard and clear hardware implementation of each of the models of cache organization. It is ...
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29 views
I'm to calculate the tag, index and offset for a given setup
Total Memory size = 65,536 bytes
Number of cache blocks = 32 cache blocks
Cache size = total 512 bytes
So using this info provided I cannot figure out how to calculate the cache block number.
I know ...
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1answer
43 views
Cache Miss and Processor Speed
today in my class my professor mentioned that
Cache misses becomes more expensive as the speed of the processor increases
But he didn't explain the reason. I ...
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1answer
161 views
Find main memory location in cache(direct mapping)
Consider main memory of the size 64 kB with each word being 8 bits(one byte) only and a direct mapping Cache memory of size 4 kB also having data word size 8 bits.
Find the following :
Find the size ...
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1answer
97 views
How does the cache / memory know where to return results of read requests to?
The pipeline of a modern processor has many stages that may issue read
requests to main memory, e.g. in fetching the next command or loading
some memory location into a register. How is the result of ...
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1answer
107 views
Computing average access time
A computer has a cache memory and a main memory with the following features:
- Memory cache access time: 4 ns
- Main memory access time: 80 ns
- The time ...
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1answer
72 views
Virtual Memory vs Cache for block identification
Both are based on the principle of locality. Then why virtual memory uses table lookup while cache memory uses associative memory for block identification?
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Cache write misses
I've been using Intel Pin tool to perform analysis of cache miss rates of a parallel application in multi-level caches, using one of the examples allcache.cpp, the results differentiate load and write ...
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2answers
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How does a cache handle overwriting between 2 addresses in the same block?
Consider a byte-addressable cache with block size 16 bytes, bytes 0-15 form one block.
First I write an int(let's say 7) to address 0, so now bytes 0-3 contain the int 7. Now if I try to write another ...
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1answer
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Average access time in two level cache system
In a two-level cache system, the level one cache has a hit time of 1 ns (inside the CPU), hit rate of 90%, and a miss penalty of 20 ns. The level two cache has a hit rate of 95% and a miss penalty of ...
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Size of the data bus connecting CPU cache and RAM?
I'm reading about CPU caches and I read that typically, cache line sizes start from 32 bytes. Since memory is slower than CPU caches therefore data is frequently loaded from the RAM into the cache and ...
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2answers
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Dynamic selection of cache replacement policy
There are some different cache replacement policies could be implemented in CPU. As far as I know, ones have better hit ratio on specific type of code than others, but if that type changes (for ...
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3answers
102 views
Does RAM get an indication of data size required
Pre-information:
I'm sure someone has asked something along these lines, but no matter how I word it, I can't seem to find a definitive answer
Question:
Does RAM get some kind of indication as to ...
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25 views
64 byte cache block and memory overhead for cachline with 7 states (3 bits)
I came across some lecture notes of a professor about memory consistency and models. There is an example about memory overhead:
The cache line has 7 states (3 bits): unowned, shared, exclusive, ...
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1answer
22 views
Reactiveness, cpu and caches
I was messing around with a reactive-based frameworks and found it very expressive. Unfortunately, most of them are using techniques that are not very efficient on CPU cashing mechanism such as ...
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1answer
25 views
Operating System code suffers more cache misses than user code
I was going through the text of the book Computer Architecture: A Quantitative Approach. It has a section in Chapter 5 where it discusses the fact that OS code undergoes more cache misses as compared ...
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1answer
52 views
Is PREFETCH an asynchronous operation?
I often hear Prefetching as a technique for speeding up, for example, sequential memory access pattern. The prefetch should occur sufficiently far ahead in time to mitigate the latency of memory ...
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1answer
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Associative mapped cache, word addressable
I have an associative mapped cache with 10 tag bits and an offset of 7bits.
What is the size of each main memory block in words(word addressable) and main memory size in words?
i worked it out as:
...
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Approximate cache size & cache line size from optimal tile size
I wrote a program that multiplies two $N\times N$ matrices represented as 2D arrays by tiling the matrices into subsets with variable tile size. Each matrix element is an 8-Byte integer. I tested the ...
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Cache mapping calculation
A cache has following specifications:
Block size = 16 Bytes
Set size = 2 way set associative
Number of sets = 128
Physical address = 23 bits, byte addressable
My Questions are:
1) How many blocks ...
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1answer
53 views
Slowdown when accessing data at page boundaries?
Hi I have a program which accesses memory words that are located X bytes apart in virtual address space. For instance, ...
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0answers
69 views
Why isn't a valid bit used for associative cache in processors
Direct map cache uses a valid bit to effectively know if any data is present to a specific cache-slot (aka line/index). If this is the only use of this bit, then I believe, once a line has v-bit set, ...
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3answers
907 views
Is CPU Registers part of Primary Memory?
A friend of mine appeared in an exam recently, and one of the question asked was regarding CPU Registers, which has two points:
(a) CPU Registers are part of Primary Memory
(b) They are volatile
And ...
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1answer
139 views
Clarification on interplay between cache line size and read/write sizes
Say that you have cache lines with the size of 64 bytes and a set-associative or directly mapped cache. Let's also say that the word size is 8 bytes.
According to my understanding, we use a number ...
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4answers
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Compiler instructions to sync core caches: are they really needed?
I have read reviews of this book, and quote the following from one of the reviews (emphasis mine):
Other than straining your eyes with old-styled C++, you can read such
misconceptions in the book ...
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1answer
206 views
What uses have been proposed for overlaid skewed associativity?
In "Concurrent Support of Multiple Page Sizes On a Skewed Associative TLB" (2004; PDF), André Seznec proposed using overlaid ways with different indexing functions with guaranteed avoidance of bank ...
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1answer
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Total bits required for a direct-mapped cache
I'm taking a course in computer architecture in which the main reference is the Computer Organization and Design by Patterson and Hennessy. I came across an example which I couldn't grasp its answer:
...
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1answer
797 views
L1 and Ln cache: when are they written?
I have been following the "High Performance Computer Architecture" course from Georgia Tech (also on YouTube), and unless I've missed something, I cannot see where the following has been explained:
...
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1answer
239 views
Finding size of cache in blocks
Let's say I have a 64 kB Cache provided (i,e 2^18) which is direct mapped and block size is 16 byte = 2^5
Now, in the solution it says
...
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1answer
5k views
Calculate number of cache lines per set or cache size
How can I calculate the number of cache lines per set or the cache size with the given information?
m (number of physical address bits): 32
C (cache size): unknown
B (Block size in bytes): 32
E (...
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1answer
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How to calculate a direct mapped chace capacity with tag and valid bits?
I've seen some very useful posts about this, but none took into consideration both the tag and valid bits. This is a question I took from a notebook in my computer engineering course.
Consider a ...
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1answer
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What's the difference between cache miss penalty and latency to memory?
Can I say that cache miss penalty includes latency to memory? My current understanding is that cache miss penalty is the time moving data from the layer closer to main memory to it. But I'm not sure ...
