Questions tagged [cpu-cache]
A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.
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Total bits required for a direct-mapped cache
I'm taking a course in computer architecture in which the main reference is the Computer Organization and Design by Patterson and Hennessy. I came across an example which I couldn't grasp its answer: ...
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1answer
203 views
L1 and Ln cache: when are they written?
I have been following the "High Performance Computer Architecture" course from Georgia Tech (also on YouTube), and unless I've missed something, I cannot see where the following has been explained:
...
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31 views
Finding size of cache in blocks
Let's say I have a 64 kB Cache provided (i,e 2^18) which is direct mapped and block size is 16 byte = 2^5
Now, in the solution it says
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Calculate number of cache lines per set or cache size
How can I calculate the number of cache lines per set or the cache size with the given information?
m (number of physical address bits): 32
C (cache size): unknown
B (Block size in bytes): 32
E (...
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1answer
124 views
How to calculate a direct mapped chace capacity with tag and valid bits?
I've seen some very useful posts about this, but none took into consideration both the tag and valid bits. This is a question I took from a notebook in my computer engineering course.
Consider a ...
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1answer
119 views
What's the difference between cache miss penalty and latency to memory?
Can I say that cache miss penalty includes latency to memory? My current understanding is that cache miss penalty is the time moving data from the layer closer to main memory to it. But I'm not sure ...
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Associative cache finding the tag and word number
An associative cache has a block size of 16 words. The capacity of the cache is 32 Kbytes and main memory can store 4 Mbytes. The word (the addressable unit) size is 2 bytes.
I'm unsure how to find ...
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58 views
Number of MUX required for Cache Mapping
I have read that the number of multiplexers required is equal to the number of bits in the TAG field. Is it true? If yes then why?
I know that the size of each multiplexer has to be S to 1, where S ...
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29 views
Relating L1 cache, TLB and main memory
Earlier while solving problems from computer organization book by Stallings, I came across the fact that
$T_a=(H_{L1})(T_{C1})+(1-H_{L1})(T_{C1}+T_M)$
where,
$T_a \rightarrow$ Average access ...
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1answer
19 views
How to count stores in cache analysis of matrix multiplication
I'm trying to understand cache misses/iter and came across this that I couldn't understand or reason out.
For ijk iteration, my slides say that there are 2 loads and 0 stores.
...
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40 views
cache coherence: false sharing vs. memory coalescing CPU vs GPU
False sharing is defined on CPU as when atleast two cores write to the same cache line. If the two cores have their own private caches, one will invalidate the other's cache line when they write to ...
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2answers
133 views
How many words of memory map to the same cache entry?
I am going over some practice questions for the Major field exam and it asks:
A processor with a word-addressable memory has a two-way set-associative cache. A cache line is one word, so a cache ...
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1answer
401 views
Architecture - calculating miss penalty
I know that AVG Memory Access Time = Hit time + Miss Rate * Miss Penalty
If I am given the AMAT and miss rate, aswell as the latency to access memory(call this x) ...
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1answer
2k views
Cache effective access time calculation
In order to calculate the effective access time of a memory sub-system, I see some different approaches, a.k.a formulas. All are reasonable, but I don't know how they differ and what is the correct ...
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2answers
76 views
what is the meaning of hit time?
Average memory access time = Hit time + Miss rate * miss penalty
Assume a computer with only one cache level. What is the exact meaning of hit time? Is it the ...
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3answers
97 views
Loading a word from byte-addressable cache
I have asked a similar question at stack-overflow, but then I found this question here, and figured it should go here instead..
So, my question is pretty much the same as the one in the question I ...
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191 views
Calculating miss rate for 2 way set associative cache
From my homework:
Consider a 2-way set-associative cache with eight 32-byte blocks. Instructions and operands are 32-bits. There are an 8- bit data bus and a 16-bit address bus. A sample code is ...
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Cache mapping problem
Okay.I have problem about cache mapping. Here is the problem .
Memory size is 1 MB
Byte addresable
Cache block size is 16 Bytes.
Cache size is 64kb
Since memory is 1 mb=2**20 Bytes.
So we need ...
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1answer
36 views
How does cache partitioning prevent covert/side-channel attacks?
In a report on an open-source separation kernel (Muen kernel) I was reading,
in the future work section, it says that cache coloring can be implemented to prevent covert/side-channel attacks.
It is ...
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231 views
Cache Hit or miss
Asume 512 Bytes direct-mapped cache with 64 Byte cache blocks (cache line size), is empty at the beginning and below given set of physical addresses are referred by CPU in the given order. At each ...
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423 views
Set Associative Cache Exercises
I am trying to solve an exercise on set-associative cache , i struggled with it for a while but i think that i figured out the answer , would be helpful if someone could check if my solution is ...
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1answer
283 views
Byte/word addressing in cache
When dealing with caches, the address is split in three parts - offset, index and tag. Question is: if we are given a word address, do we first have to shift left by 2 bits by adding 00 at the end of ...
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75 views
Computer Architecture: Hit ratio with address
There is a problem that as much as I am trying to understand it, I fail. There are theoretically three cache manufacturers that each make 16 byte cache. The first has 16 blocks, 8 blocks the second, ...
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MESI protocol and write to Main Memory
I am studying cache coherence MESI protocol with "intervention" (cache can send to other cache without use the Main Memory).
On my notes I wrote that in case of a processor has a block in M (modified ...
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1answer
34 views
Word arrangement in caches
Why are the words in a cache line adjacent to one another?
Does this arrangement improve reading/writing performance or are there other reasons to justify this choice?
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Trouble with Direct Mapping for Caches
I have an online homework assignment that is asking me for the tag and index in a direct-mapped cache, for a series of memory addresses. The cache is specified to have 16 one word blocks.
One of the ...
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Find the total number of bytes for a direct mapping cache to store 512kb of data in 4 words blocks assuming a 32-bit address and word addressing
This question was given in a practice exam by my professor and she never told us how to do it nor the answer. Can someone please explain it for me? Thank you in advance.
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How to find number of blocks in cache?
Suppose a computer using direct mapped cache has 512KB of main memory and a cache of 4 Bytes, where each cache size is 64KB.
1)Find Number of blocks in cache.
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1answer
5k views
A cache memory has a line size of eight 64-bit words and a capacity of 4K words
A cache memory has a line size of eight 64-bit words and a capacity of 4K words. The main memory size that is cacheable is 1024 Mbits. Assuming that the addressing is done at the byte level, show ...
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42 views
TLB failure in a memory access
I have come across a question which says
If there is a TLB failure in a memory access, the disk must be accessed to load a new page into main memory.
The answer is NO, but i dont understand why. Is ...
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2answers
82 views
How is an OS page stored in a k-way set-associative cache?
I have been reading about set-associative caches. As far as I have read, in case of n-way set-associative cache each way stores, a block (let's say 16 bytes) and therefore each set will be of size 16n ...
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1answer
86 views
Is finding cache size possible with information given?
An 8-way set-associative cache is used in a computer in which the real memory size is 222 bytes. The line size is 16 bytes, and there are 26 lines per set.
A) What is the size of the cache in bytes?
...
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1answer
796 views
2-way set associative cache exercise
In the exercise I have a 32 bit processor with a 2-way set associative cache. I have 32 bit addresses: 31-14 tag, 13-5 index, 4-0 offset.
Calculate:
1) Cache line size in number of words (1 word = 4 ...
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2answers
55 views
structure of cache when CPU uses words smaller than the main memory
As the title says, i have the following excersice:
An associative mapping cache with four lines in each set, can store in each line two words of 16 bits each. It can store 4K words, that they have ...
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1answer
1k views
Calculating Tag Bits in a Direct-Mapped Cache
The following comes from Patterson & Hennessy Computer Org. and Design (5th ed., p. 390):
How many total bits are required for a direct-mapped cache with 16 KiB
of data and 4-word blocks, ...
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2answers
42 views
Whats the point of caching if the minimum single clock cycle time is the prorogation delay of the slowest component (fetching from DRAM)?
I know that the clock speed is determined by the slowest stage within the processor (usually fetch) because one clock cycle will take as much time as the slowest pipeline stage to ensure everything is ...
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How is there a CPU read misses on exclusive caches?
If the lower level cache contains blocks that are not present in the higher level cache or other caches then it is said to be exclusive.
It is exclusive because it is only there. How can there be ...
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1answer
137 views
When LRU is NOT the optimal replacement policy
I've been googling this topic but still couldnt get a legit answer. So can someone explain with some examples that if we were to use cache memory instead of LRU we would have lower miss rate (better ...
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37 views
Through how many levels must cache writeback propagate?
Suppose that my multicore computer system has the diagrammed memory caches.
...
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2answers
444 views
Why page size = size of one cache way?
Why is that the page size equals the size of one cache way?
My book states "A direct-mapped cache cannot be bigger than a page".
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348 views
Physically indexed virtually tagged cache
PIVT cache is indexed physically so address translation using TLB is needed to get into cache and we use virtual address as the tag for comparison .
I read that homonym is a problem which is caused ...
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1answer
2k views
What is the difference between caching, buffering and paging? Expecting a detailed answer on the OS level
I have been reading about caching and buffering it seems about the same to me can't get hold of the differences clearly and paging, for now the only difference I understand between paging and caching ...
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1answer
315 views
CPU cache - retrieving data from memory
Regarding CPU cache, if the CPU does not find the data it needs in the cache, I understand it then looks for it in the main memory (RAM). (Let's assume we have only one level of cache in order to keep ...
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1answer
5k views
Hit/Miss in a 2-way set associative cache with offset
"In a 2-way set associative cache of 4 blocks containing 4 words each, which one of these addresses will return a hit when being read? The blocks to be retained in the cache are decided by LRU."
4 ...
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1answer
1k views
What is Memory Mapping in Cache?
People all over the internet are asking "What are the different Memory Mapping Techniques in Cache", but i couldn't find anywhere the answer to "What is Memory Mapping exactly?".
Please tell what do ...
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1answer
2k views
Calculate Miss rate of L2 cache given global and L1 miss rates
If I have a Global miss rate of all caches of a total of 5.41% and the miss rate of a single level cache of 9.13%, how can I effectively calculate how much the second level cache miss rate need to be?
...
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2answers
518 views
how os can calculate cpu cache size?
There's an interview question.
In my opinion, os can calculate cache hit rate and miss rate(with the total running time of process and the number of transfer of block of memory to cache).
But how can ...
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402 views
Which of the following cache designer guidelines are generally valid?
Which of the following cache designer guidelines are generally valid?
The shorter the memory latency, the smaller the cache block
The shorter the memory latency, the larger the cache block
The higher ...
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1answer
80 views
Calculating fractions of accesses from various levels of memory? (L2 - Main)
I'm currently studying computer architectures module, and during the workshop I came a across a series of questions that I struggled to being to answer.
The question goes;
...
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60 views
Principle of locality for object-key data pairs
It seems that if we only have object-key cache then we won't have spatial locality and only temporal locality. I use memcached in a python application and that has only object-key pairs and no ...
