Questions tagged [cpu-cache]
A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.
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questions
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Whats the formula for finding the tag bits in set associative mapped?
Is it ---- log (base 2)Main memory size/cache size
ot it is
log(base 2)((Main memory size/cache size)*k ) where k is kth set associative
Recently i watched a tutorial and i got confused that which ...
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2answers
30 views
Dynamic selection of cache replacement policy
There are some different cache replacement policies could be implemented in CPU. As far as I know, ones have better hit ratio on specific type of code than others, but if that type changes (for ...
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3answers
76 views
Does RAM get an indication of data size required
Pre-information:
I'm sure someone has asked something along these lines, but no matter how I word it, I can't seem to find a definitive answer
Question:
Does RAM get some kind of indication as to ...
0
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0answers
21 views
64 byte cache block and memory overhead for cachline with 7 states (3 bits)
I came across some lecture notes of a professor about memory consistency and models. There is an example about memory overhead:
The cache line has 7 states (3 bits): unowned, shared, exclusive, ...
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1answer
21 views
Reactiveness, cpu and caches
I was messing around with a reactive-based frameworks and found it very expressive. Unfortunately, most of them are using techniques that are not very efficient on CPU cashing mechanism such as ...
0
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1answer
21 views
Operating System code suffers more cache misses than user code
I was going through the text of the book Computer Architecture: A Quantitative Approach. It has a section in Chapter 5 where it discusses the fact that OS code undergoes more cache misses as compared ...
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0answers
13 views
Direct mapped cache example
i am really confused on the topic Direct Mapped Cache i've been looking around for an example with a good explanation and it's making me more confused then ever.
For example: I have
2048 byte ...
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0answers
32 views
Calculating effective access time in memory caching context
I have went through various problems involving time required to access required data in the context of caching.
They use different formulae in different problems. For example, this answer suggests ...
3
votes
1answer
36 views
Is PREFETCH an asynchronous operation?
I often hear Prefetching as a technique for speeding up, for example, sequential memory access pattern. The prefetch should occur sufficiently far ahead in time to mitigate the latency of memory ...
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1answer
149 views
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12 views
Question on Cache Size
I'm having trouble understanding this particular problem.
So given that:
Cache size in bytes = 4096
The number of cache lines = 64
The cache block size in bites = 64
The number of main memory ...
0
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0answers
35 views
Associative mapped cache, word addressable
I have an associative mapped cache with 10 tag bits and an offset of 7bits.
What is the size of each main memory block in words(word addressable) and main memory size in words?
i worked it out as:
...
0
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0answers
8 views
Study of cache behaviour of algorithms on Virtualbox
I want to study certain cache oblivious algorithms and cache behaviour of some other algorithms I wrote in general.
I want to understand, is it advisable, if I do this study in an virtualized ...
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0answers
12 views
Relationship between associativity, number of sets, block size and cache inclusion policy
I'm studying for an exam and I came across a couple of questions asking me to argue whether cache inclusion is guaranteed or not. I read Wikipedia and wikipedia claims cache inclusion is possible if ...
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0answers
12 views
Approximate cache size & cache line size from optimal tile size
I wrote a program that multiplies two $N\times N$ matrices represented as 2D arrays by tiling the matrices into subsets with variable tile size. Each matrix element is an 8-Byte integer. I tested the ...
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0answers
12 views
What happen if the L1 cache has the address entry with write_back attribute. Will that address be available in L2 cache?
I have the TLB entry for a particular address. This address has write-back attributes in both L1 cache and L2 cache.
My queries are:
1> if L1 cache entry has write-back, can it be write-back in L2?
2> ...
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0answers
52 views
Finding Cache Miss Penalty in Memoery with Banks
Following the same argument we compute the miss rate as 1/2Consider a memory
system with 4 Gbyte of main memory, and a 256 Kbyte direct mapped cache with 128
byte lines. The main memory system ...
0
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0answers
38 views
Cache mapping calculation
A cache has following specifications:
Block size = 16 Bytes
Set size = 2 way set associative
Number of sets = 128
Physical address = 23 bits, byte addressable
My Questions are:
1) How many blocks ...
0
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0answers
181 views
AMAT using Local miss rate, global miss rate, local hit rate, global hit rate
Consider the following scenario as shown in image:
I have summarized the above Memory layout in terms of Miss rates and hit rates:
...
0
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0answers
72 views
Need help understanding set-associative cache
The problem I'm trying to solve is:
A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main ...
1
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1answer
44 views
Slowdown when accessing data at page boundaries?
Hi I have a program which accesses memory words that are located X bytes apart in virtual address space. For instance, ...
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0answers
50 views
Why isn't a valid bit used for associative cache in processors
Direct map cache uses a valid bit to effectively know if any data is present to a specific cache-slot (aka line/index). If this is the only use of this bit, then I believe, once a line has v-bit set, ...
0
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3answers
238 views
Is CPU Registers part of Primary Memory?
A friend of mine appeared in an exam recently, and one of the question asked was regarding CPU Registers, which has two points:
(a) CPU Registers are part of Primary Memory
(b) They are volatile
And ...
1
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1answer
60 views
Clarification on interplay between cache line size and read/write sizes
Say that you have cache lines with the size of 64 bytes and a set-associative or directly mapped cache. Let's also say that the word size is 8 bytes.
According to my understanding, we use a number ...
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4answers
105 views
Compiler instructions to sync core caches: are they really needed?
I have read reviews of this book, and quote the following from one of the reviews (emphasis mine):
Other than straining your eyes with old-styled C++, you can read such
misconceptions in the book ...
1
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1answer
187 views
What uses have been proposed for overlaid skewed associativity?
In "Concurrent Support of Multiple Page Sizes On a Skewed Associative TLB" (2004; PDF), André Seznec proposed using overlaid ways with different indexing functions with guaranteed avoidance of bank ...
0
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0answers
430 views
Total bits required for a direct-mapped cache
I'm taking a course in computer architecture in which the main reference is the Computer Organization and Design by Patterson and Hennessy. I came across an example which I couldn't grasp its answer: ...
3
votes
1answer
509 views
L1 and Ln cache: when are they written?
I have been following the "High Performance Computer Architecture" course from Georgia Tech (also on YouTube), and unless I've missed something, I cannot see where the following has been explained:
...
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1answer
73 views
Finding size of cache in blocks
Let's say I have a 64 kB Cache provided (i,e 2^18) which is direct mapped and block size is 16 byte = 2^5
Now, in the solution it says
...
0
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1answer
1k views
Calculate number of cache lines per set or cache size
How can I calculate the number of cache lines per set or the cache size with the given information?
m (number of physical address bits): 32
C (cache size): unknown
B (Block size in bytes): 32
E (...
0
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1answer
628 views
How to calculate a direct mapped chace capacity with tag and valid bits?
I've seen some very useful posts about this, but none took into consideration both the tag and valid bits. This is a question I took from a notebook in my computer engineering course.
Consider a ...
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1answer
2k views
What's the difference between cache miss penalty and latency to memory?
Can I say that cache miss penalty includes latency to memory? My current understanding is that cache miss penalty is the time moving data from the layer closer to main memory to it. But I'm not sure ...
0
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1answer
323 views
Number of MUX required for Cache Mapping
I have read that the number of multiplexers required is equal to the number of bits in the TAG field. Is it true? If yes then why?
I know that the size of each multiplexer has to be S to 1, where S ...
0
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1answer
29 views
How to count stores in cache analysis of matrix multiplication
I'm trying to understand cache misses/iter and came across this that I couldn't understand or reason out.
For ijk iteration, my slides say that there are 2 loads and 0 stores.
...
0
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2answers
352 views
How many words of memory map to the same cache entry?
I am going over some practice questions for the Major field exam and it asks:
A processor with a word-addressable memory has a two-way set-associative cache. A cache line is one word, so a cache ...
0
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1answer
2k views
Architecture - calculating miss penalty
I know that AVG Memory Access Time = Hit time + Miss Rate * Miss Penalty
If I am given the AMAT and miss rate, aswell as the latency to access memory(call this x) ...
2
votes
1answer
10k views
Cache effective access time calculation
In order to calculate the effective access time of a memory sub-system, I see some different approaches, a.k.a formulas. All are reasonable, but I don't know how they differ and what is the correct ...
0
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2answers
1k views
what is the meaning of hit time?
Average memory access time = Hit time + Miss rate * miss penalty
Assume a computer with only one cache level. What is the exact meaning of hit time? Is it the ...
0
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3answers
397 views
Loading a word from byte-addressable cache
I have asked a similar question at stack-overflow, but then I found this question here, and figured it should go here instead..
So, my question is pretty much the same as the one in the question I ...
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vote
0answers
280 views
Calculating miss rate for 2 way set associative cache
From my homework:
Consider a 2-way set-associative cache with eight 32-byte blocks. Instructions and operands are 32-bits. There are an 8- bit data bus and a 16-bit address bus. A sample code is ...
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0answers
77 views
Cache mapping problem
Okay.I have problem about cache mapping. Here is the problem .
Memory size is 1 MB
Byte addresable
Cache block size is 16 Bytes.
Cache size is 64kb
Since memory is 1 mb=2**20 Bytes.
So we need ...
5
votes
1answer
72 views
How does cache partitioning prevent covert/side-channel attacks?
In a report on an open-source separation kernel (Muen kernel) I was reading,
in the future work section, it says that cache coloring can be implemented to prevent covert/side-channel attacks.
It is ...
1
vote
0answers
381 views
Cache Hit or miss
Asume 512 Bytes direct-mapped cache with 64 Byte cache blocks (cache line size), is empty at the beginning and below given set of physical addresses are referred by CPU in the given order. At each ...
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0answers
729 views
Set Associative Cache Exercises
I am trying to solve an exercise on set-associative cache , i struggled with it for a while but i think that i figured out the answer , would be helpful if someone could check if my solution is ...
1
vote
1answer
667 views
Byte/word addressing in cache
When dealing with caches, the address is split in three parts - offset, index and tag. Question is: if we are given a word address, do we first have to shift left by 2 bits by adding 00 at the end of ...
0
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0answers
120 views
Computer Architecture: Hit ratio with address
There is a problem that as much as I am trying to understand it, I fail. There are theoretically three cache manufacturers that each make 16 byte cache. The first has 16 blocks, 8 blocks the second, ...
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0answers
161 views
MESI protocol and write to Main Memory
I am studying cache coherence MESI protocol with "intervention" (cache can send to other cache without use the Main Memory).
On my notes I wrote that in case of a processor has a block in M (modified ...
1
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1answer
34 views
Word arrangement in caches
Why are the words in a cache line adjacent to one another?
Does this arrangement improve reading/writing performance or are there other reasons to justify this choice?
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0answers
89 views
Trouble with Direct Mapping for Caches
I have an online homework assignment that is asking me for the tag and index in a direct-mapped cache, for a series of memory addresses. The cache is specified to have 16 one word blocks.
One of the ...
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0answers
61 views
How to find number of blocks in cache?
Suppose a computer using direct mapped cache has 512KB of main memory and a cache of 4 Bytes, where each cache size is 64KB.
1)Find Number of blocks in cache.
