Questions tagged [cpu-cache]

A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.

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direct-mapped cache

problem is as follow: For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. (1 word = 64-bits) Tag: 63-10 Index: 9-5 Offset: 4-0 I ...
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How are replacement policies implemented?

Suppose there is a set-associative cache using LRU or ARC replacement policy. What implements these policies? Is it a hardware module or is there a soft doing this?
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Computing average access time

A computer has a cache memory and a main memory with the following features: - Memory cache access time: 4 ns - Main memory access time: 80 ns - The time ...
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Virtual Memory vs Cache for block identification

Both are based on the principle of locality. Then why virtual memory uses table lookup while cache memory uses associative memory for block identification?
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Cache write misses

I've been using Intel Pin tool to perform analysis of cache miss rates of a parallel application in multi-level caches, using one of the examples allcache.cpp, the results differentiate load and write ...
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How does a cache handle overwriting between 2 addresses in the same block?

Consider a byte-addressable cache with block size 16 bytes, bytes 0-15 form one block. First I write an int(let's say 7) to address 0, so now bytes 0-3 contain the int 7. Now if I try to write another ...
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Average access time in two level cache system

In a two-level cache system, the level one cache has a hit time of 1 ns (inside the CPU), hit rate of 90%, and a miss penalty of 20 ns. The level two cache has a hit rate of 95% and a miss penalty of ...
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Size of the data bus connecting CPU cache and RAM?

I'm reading about CPU caches and I read that typically, cache line sizes start from 32 bytes. Since memory is slower than CPU caches therefore data is frequently loaded from the RAM into the cache and ...
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If there is a cache miss can we consider extra memory accesses because it has to fetch data from the main memory?

A program, when run on a processor with unified cache (Data and Instructions in same cache) results in 0.05 cache misses per instruction. Also 25% of overall instructions of the program are load/store ...
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Which state change in the MESI state machine covers the case of replacing a modified cache line with another newly read line?

I'm reading an article on the MESI protocol entitled Memory Barriers: a Hardware View for Software Hackers and I'm having trouble figuring out which state transition corresponds to the situation when ...
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Dynamic selection of cache replacement policy

There are some different cache replacement policies could be implemented in CPU. As far as I know, ones have better hit ratio on specific type of code than others, but if that type changes (for ...
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Does RAM get an indication of data size required

Pre-information: I'm sure someone has asked something along these lines, but no matter how I word it, I can't seem to find a definitive answer Question: Does RAM get some kind of indication as to ...
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64 byte cache block and memory overhead for cachline with 7 states (3 bits)

I came across some lecture notes of a professor about memory consistency and models. There is an example about memory overhead: The cache line has 7 states (3 bits): unowned, shared, exclusive, ...
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Reactiveness, cpu and caches

I was messing around with a reactive-based frameworks and found it very expressive. Unfortunately, most of them are using techniques that are not very efficient on CPU cashing mechanism such as ...
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Operating System code suffers more cache misses than user code

I was going through the text of the book Computer Architecture: A Quantitative Approach. It has a section in Chapter 5 where it discusses the fact that OS code undergoes more cache misses as compared ...
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Direct mapped cache example

i am really confused on the topic Direct Mapped Cache i've been looking around for an example with a good explanation and it's making me more confused then ever. For example: I have 2048 byte ...
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Calculating effective access time in memory caching context

I have went through various problems involving time required to access required data in the context of caching. They use different formulae in different problems. For example, this answer suggests ...
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Is PREFETCH an asynchronous operation?

I often hear Prefetching as a technique for speeding up, for example, sequential memory access pattern. The prefetch should occur sufficiently far ahead in time to mitigate the latency of memory ...
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Question on Cache Size

I'm having trouble understanding this particular problem. So given that: Cache size in bytes = 4096 The number of cache lines = 64 The cache block size in bites = 64 The number of main memory ...
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Associative mapped cache, word addressable

I have an associative mapped cache with 10 tag bits and an offset of 7bits. What is the size of each main memory block in words(word addressable) and main memory size in words? i worked it out as: ...
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Study of cache behaviour of algorithms on Virtualbox

I want to study certain cache oblivious algorithms and cache behaviour of some other algorithms I wrote in general. I want to understand, is it advisable, if I do this study in an virtualized ...
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Relationship between associativity, number of sets, block size and cache inclusion policy

I'm studying for an exam and I came across a couple of questions asking me to argue whether cache inclusion is guaranteed or not. I read Wikipedia and wikipedia claims cache inclusion is possible if ...
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Approximate cache size & cache line size from optimal tile size

I wrote a program that multiplies two $N\times N$ matrices represented as 2D arrays by tiling the matrices into subsets with variable tile size. Each matrix element is an 8-Byte integer. I tested the ...
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What happen if the L1 cache has the address entry with write_back attribute. Will that address be available in L2 cache?

I have the TLB entry for a particular address. This address has write-back attributes in both L1 cache and L2 cache. My queries are: 1> if L1 cache entry has write-back, can it be write-back in L2? 2> ...
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Finding Cache Miss Penalty in Memoery with Banks

Following the same argument we compute the miss rate as 1/2Consider a memory system with 4 Gbyte of main memory, and a 256 Kbyte direct mapped cache with 128 byte lines. The main memory system ...
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Cache mapping calculation

A cache has following specifications: Block size = 16 Bytes Set size = 2 way set associative Number of sets = 128 Physical address = 23 bits, byte addressable My Questions are: 1) How many blocks ...
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AMAT using Local miss rate, global miss rate, local hit rate, global hit rate

Consider the following scenario as shown in image: I have summarized the above Memory layout in terms of Miss rates and hit rates: ...
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Need help understanding set-associative cache

The problem I'm trying to solve is: A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main ...
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Slowdown when accessing data at page boundaries?

Hi I have a program which accesses memory words that are located X bytes apart in virtual address space. For instance, ...
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Why isn't a valid bit used for associative cache in processors

Direct map cache uses a valid bit to effectively know if any data is present to a specific cache-slot (aka line/index). If this is the only use of this bit, then I believe, once a line has v-bit set, ...
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Is CPU Registers part of Primary Memory?

A friend of mine appeared in an exam recently, and one of the question asked was regarding CPU Registers, which has two points: (a) CPU Registers are part of Primary Memory (b) They are volatile And ...
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Clarification on interplay between cache line size and read/write sizes

Say that you have cache lines with the size of 64 bytes and a set-associative or directly mapped cache. Let's also say that the word size is 8 bytes. According to my understanding, we use a number ...
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Compiler instructions to sync core caches: are they really needed?

I have read reviews of this book, and quote the following from one of the reviews (emphasis mine): Other than straining your eyes with old-styled C++, you can read such misconceptions in the book ...
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What uses have been proposed for overlaid skewed associativity?

In "Concurrent Support of Multiple Page Sizes On a Skewed Associative TLB" (2004; PDF), André Seznec proposed using overlaid ways with different indexing functions with guaranteed avoidance of bank ...
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Total bits required for a direct-mapped cache

I'm taking a course in computer architecture in which the main reference is the Computer Organization and Design by Patterson and Hennessy. I came across an example which I couldn't grasp its answer: ...
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L1 and Ln cache: when are they written?

I have been following the "High Performance Computer Architecture" course from Georgia Tech (also on YouTube), and unless I've missed something, I cannot see where the following has been explained: ...
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Finding size of cache in blocks

Let's say I have a 64 kB Cache provided (i,e 2^18) which is direct mapped and block size is 16 byte = 2^5 Now, in the solution it says ...
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Calculate number of cache lines per set or cache size

How can I calculate the number of cache lines per set or the cache size with the given information? m (number of physical address bits): 32 C (cache size): unknown B (Block size in bytes): 32 E (...
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How to calculate a direct mapped chace capacity with tag and valid bits?

I've seen some very useful posts about this, but none took into consideration both the tag and valid bits. This is a question I took from a notebook in my computer engineering course. Consider a ...
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What's the difference between cache miss penalty and latency to memory?

Can I say that cache miss penalty includes latency to memory? My current understanding is that cache miss penalty is the time moving data from the layer closer to main memory to it. But I'm not sure ...
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Number of MUX required for Cache Mapping

I have read that the number of multiplexers required is equal to the number of bits in the TAG field. Is it true? If yes then why? I know that the size of each multiplexer has to be S to 1, where S ...
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How to count stores in cache analysis of matrix multiplication

I'm trying to understand cache misses/iter and came across this that I couldn't understand or reason out. For ijk iteration, my slides say that there are 2 loads and 0 stores. ...
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How many words of memory map to the same cache entry?

I am going over some practice questions for the Major field exam and it asks: A processor with a word-addressable memory has a two-way set-associative cache. A cache line is one word, so a cache ...
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Architecture - calculating miss penalty

I know that AVG Memory Access Time = Hit time + Miss Rate * Miss Penalty If I am given the AMAT and miss rate, aswell as the latency to access memory(call this x) ...
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Cache effective access time calculation

In order to calculate the effective access time of a memory sub-system, I see some different approaches, a.k.a formulas. All are reasonable, but I don't know how they differ and what is the correct ...
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what is the meaning of hit time?

Average memory access time = Hit time + Miss rate * miss penalty Assume a computer with only one cache level. What is the exact meaning of hit time? Is it the ...
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Loading a word from byte-addressable cache

I have asked a similar question at stack-overflow, but then I found this question here, and figured it should go here instead.. So, my question is pretty much the same as the one in the question I ...
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Calculating miss rate for 2 way set associative cache

From my homework: Consider a 2-way set-associative cache with eight 32-byte blocks. Instructions and operands are 32-bits. There are an 8- bit data bus and a 16-bit address bus. A sample code is ...
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Cache mapping problem

Okay.I have problem about cache mapping. Here is the problem . Memory size is 1 MB Byte addresable Cache block size is 16 Bytes. Cache size is 64kb Since memory is 1 mb=2**20 Bytes. So we need ...

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