In a 32-bit byte addressable memory system, each "row" has 4 bytes and each byte has a 32-bit address.

My question is: can I read and/or write word of length 64 bits from/to memory? In other terms, can my word length be 8 bytes long or is the maximum number of bytes/word 4?

  • $\begingroup$ Well, what does it mean to read and/or write [eight byte words] from/to memory with "row"s of four bytes, what is the difference to transferring two four-byte (half?)words? $\endgroup$ – greybeard Feb 4 '20 at 22:58
  • $\begingroup$ Let me ask the question in a different way: can the maximum chunk of data fetched by the processor from the 32-bit memory be two 32-bit halfwords? (Hence 64 bit for a word) $\endgroup$ – OmarAI Feb 5 '20 at 4:46
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    $\begingroup$ FWIW A 32 bit x86 processor does this all the time when reading double precision floating point numbers. $\endgroup$ – gnasher729 Feb 5 '20 at 19:39

Just what makes a processor a 32-bit processor?
And what would 64-bit word/32-bit halfword mean in the context?

There are processors allowing a single instruction to read more than one "memory cell", with documentation more or less readily available. The DEC VAX is notorious for having quad- and octaword accesses (a word being half the width of the general purpose registers (and data bus of early implementations)…).
There are processors with the width of the data bus smaller than a GPR. The Motorola 68000 was dubbed a 16-bit CPU - with 32 bit GPRs from the start. Then, the were Intel 8088, 68008 with a data bus a quarter in width compared to its GPRs, …
There are (memory) buses that allow locking of consecutive transfers.
There are buses and memory interfaces (on processing units as well as on memory devices) providing for burst transfers.

  • $\begingroup$ When you say locking of consecutive transfers on the buses. Are you talking about locking as a synchronization mechanism ? $\endgroup$ – Papaya-Automaton Dec 20 '20 at 17:32
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    $\begingroup$ @Papaya-Automaton: I was thinking of multi-cell/"word" transfers and interpretation, e.g. by more than one "processing unit" concurrently. Even when it may be equivalent to use, say, the new or the old value of a "double precision variable", it rarely does to use the characteristic&most significant part of the old value and the least significant part of the new one - or vice versa. $\endgroup$ – greybeard Dec 20 '20 at 17:46

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