So, i just got through studying DRAM architecture. I learned that a row address, column address, bank number etc are provided to the DRAM during a read operation. Based on the address provided, 64 bits will be transferred back to the memory controller (assuming the data bus is 64 bits wide). So if we have 8 DRAM chips, each will contribute 8 bits to the data bus. Basically a single memory address (consisting of a row address, column address etc.) corresponds to 64 bits in the DRAM.
But then i came across the fact that most modern computer memory is byte addressable? So the CPU can request a single byte of data rather than a 64 bit chunk as is output by DRAM.
I'm not sure how to reconcile the two pieces of info. Can someone please clarify how addressing works? So if the CPU requests the byte at a certain address, how is that translated into a row address and column address to get the requested byte from DRAM, since a row and column address in DRAM returns 64 bits and not a single byte?
