Relation between size of address bus and memory size; memory Segmentation in 8086

Question

My question is related to memory segmentation in 8086. I learnt that,

8086 has a 20 bit address bus. And so it can address 2^20 different addresses. Which means it has an memory size of 2^20, i.e, 1MB.

I have a few doubts:

1. What I understand from the fact that 8086 has a 20 bit address bus is that it could have 2^20 different combinations of 0s and 1s, each of which represents one physical address. What I don't understand is that how does 2^20 different address locations mean 1 MB of addressable memory? How is total number of different addresses locations related to memory size (in Megabytes)?

2. Also, correct me if I'm wrong, the 16 bit segment registers in 8086 hold the starting address of the different segments in the memory (Code, Stack, Data, Extra).My question is, aren't the addresses in memory of 20 bits? Then how can the 16 bit register hold 20 bit addresses? If it contains the upper 16 bit of the 20 bit address, how does the processor make out to which exact address location it has to point?

P.S: I am a beginner is micro-processors and total reliant on self study, so kindly excuse if my questions seem a bit silly.

Thanks in advance.

Answer 1

As for your first question, the memory size and the address space are the same thing. The memory is composed of addresses, where each address contains a value. In the 8086, each address contains 8bit of data. Then, $2^{20}$ addresses means $2^{20}$ records of size 8bit each. As you known, $2^{20}=1$Mega and 8bit=1Byte so 20bits of address means 1Mega addresses x 8bit = 1MegaByte memory.

As for your second question, you are right - the address needs 20bits, and each register is only 16bits. So the solution is to use two registers to address each address in the memory. With 2 registers we potentially have 32bits, but the address space needs only 20, so the 8086 actually manipulates the two registers to get only 20 bits. Basically, it concatenates 4bits (all zeros) to the first register (so now it is 20bits), and adds the result to the other register. It is easy to verify that every combination of 20bits is accessible via two registers (actually, multiple combinations lead to the same address).

Answer 2

I wish to add an adjustment to the fine response by @Ran G. His explanation of what the address space is, is entirely correct. However, this matches the memory size only if each and every address is backed by memory hardware. And this is NOT necessarily the case!

Why could there be less memory hardware than can cover the address space? One trivial answer is cost: Memory hardware can be expensive, so someone wishing to sell a cheaper computer could build one with less than the maximum amount of memory hardware, and this can work because there are people out there who don't need 'that much' memory. For example, no current computer which has 64-bit addressing is ever sold with $2^{64}$ bytes worth of addressable memory (that's over a billion billion bytes!).

A more interesting reason is memory-mapped I/O. Strictly speaking, one can attach to a processor's address lines any hardware which behaves like memory hardware (with respect to the sent address and data read/write action). Normally this is of course memory hardware, but other kinds of devices can use the same protocols. For example: If one has a robot arm with motors in its several joints, plus pressure sensors on its gripper, then one can control the arm with a computer via a card which maps the signals sent to the motors and received from the sensors to specific addresses, and install that card on the computer's address lines. The advantage being that one can use ordinary instructions to control the device (i.e control becomes a pure software problem). This technique is in fact quite ubiquitous.

Answer 3

That's the beauty of cisc machines. For starters as you can see address bus is 20bit wide but resisters are 16bit wide, so microprocessor will process 16bit at a time.

Now let's answer your questions :

1) Address size has nothing to do with architecture size. You can have instructions that can map 64bit or 128 bit address space in instructions. For example mov can be hard coded in hardware itself to fetch next addressing scheme as required which eliminates requirements of same size bus and resistors. The same mov command with proper bit masking can use address of special resistors instead of memory spaces. It drills down to the choice of system architecture. Thus the name complex instruction set. It goes beyond this simple explanation, but to give an idea, instructions are flexible enough to understand addressing schemes.

So answer is no when you are storing resistor data into memory, it refers to 16bit wide data bus. It is still storing data as usual way. But micro processor can operate on 8bit, 16bit or divide 32bit operation in sub operations as well depending on instruction.

It uses segments to divide memory into usable chunks which is mapped by combing 16bit address scheme but by shifting it to 4bit and adding offset bits to get actual physical address. Modern cpu uses dedicated hardware called memory management unit having multiple operating mode of direct memory access and IO access as well.

Here's the quote :

Rather than concatenating the segment register with the address register, as in most processors whose address space exceeds their register size, the 8086 shifts the 16-bit segment only four bits left before adding it to the 16-bit offset (16×segment + offset), therefore producing a 20-bit external (or effective or physical) address from the 32-bit segment:offset pair. As a result, each external address can be referred to by 212 = 4096 different segment:offset pairs.

2) Answer to this question is linked on how 8086 translates address to segments. As you can see it doesn't add offsets immediately but directly uses address schemes to map physical address without adding extra hardware. It's a clever way of addressing and doesn't require offset as it's already mapped to stored address space which is kind of 32bit wide when you add address+offset, enough to store 4GB space which you can see in 80386 models. Making it backward compatible as well.