Do unconditional branches, such as jump/goto instructions cause control hazards? If so, why?

I am wondering because if unconditional branches did cause control hazards, that is like saying if A were the jump foo instruction and another instruction B was the first one under foo:, B would have a control dependency on A. While this is technically true, I don't see how this would cause a hazard in a pipeline since we know with 100% certainly that B will be executed since an unconditional jump instruction A preceded it.

  • $\begingroup$ What kind of hazards are you asking about? There pipeline stalls/reloads, then there are the classic programming hazard of RISC machines (branch delay slots, and load/use delays), then there is the hazard of speculative execution re: the recent Meltdown & Spectre chip bugs. $\endgroup$ – Erik Eidt Feb 8 '18 at 16:51

YES, unconditional jumps can cause a control hazard in a pipelined machine.

we know with 100% certainly that B will be executed since an unconditional jump instruction A preceded it.

Well, we know, but the CPU does not know. I mean, the CPU does know that we need to jump to B, but only after the CPU decodes the jump instruction and realizes that the instruction is a jump (to B). Until that point thee CPU did not know it is about to jump and during that period it continued inserting other instructions to the pipe (not necessarily from B).

When the CPU finds out it has a jump it is "too late": the pipe is already contaminated with other instructions.

In your example, the "contamination" is in fact the correct code, but in the general case it may a different code segment.

  • $\begingroup$ Which CPU are we talking about? A 6502 wouldn’t be sophisticated enough to have a complicated pipeline, a classic five-stage-pipeline RISC machine iike the SPARC v7 or MIPS would introduce a delay slot so that the next instruction in the pipeline will always be valid, and a modern CPU microarchitecture might do all sorts of things to try to decode the instruction early. What kind of hazards we’d get depends on what architecture we’re talking about. $\endgroup$ – Davislor Feb 8 '18 at 7:05
  • $\begingroup$ @Davislor I wasn't referring to any specific CPU but rather to a general pipelined CPU. Of course if you put delays you will be saved, and this is definitely one way to solve a control hazard. Other methods exist as well. $\endgroup$ – Ran G. Feb 8 '18 at 17:45
  • $\begingroup$ As processors advance the pipelines get longer and the once sufficient single delay slot is no longer enough, though it is now baked into the ISA (as we can't just add delay slots willy-nilly or else that is a new ISA). Thus, the pipeline hazards return... $\endgroup$ – Erik Eidt Feb 9 '18 at 1:32

Not in the sense you probably mean. An unconditional branch cannot be mispredicted, and most architectures would be designed to avoid delays, such as by prefetching. Some ISAs even introduced mechanisms such as a delay slot to keep the pipeline full.

In a broad sense, sure, it could happen: for example, if a given CPU doesn’t have the next instruction to be executed in its cache, it needs to wait. One situation where this might come up is if a JIT compiler needs to write out some instructions and then run them, possibly on another core.

  • $\begingroup$ I guess in a general sense of what you are saying, a jump instruction requires a fetch of the operand that has the jump destination, so I suppose we couldn't fetch the instruction after the jump until the jump address was resolved. $\endgroup$ – jshapy8 Feb 8 '18 at 1:21
  • $\begingroup$ A given ISA might or might not allow the kind of operand that would cause that problem. RISC CPUs typically would not, but if you could jump to the address stored in the address of the operand, then yes. Or if a given CPU doesn’t prefetch. $\endgroup$ – Davislor Feb 8 '18 at 1:23
  • $\begingroup$ A specific example might be the fence instruction RISC-V requires before calling modified code. $\endgroup$ – Davislor Feb 8 '18 at 1:26
  • $\begingroup$ I would assume that instructions after the jump would be going through the pipeline, but would have to be aborted once we know we are supposed to jump somewhere else. So the instruction that is jumped to would be dependent on the jump instruction because it would have to stall until the jump instruction is decoded and fetched $\endgroup$ – jshapy8 Feb 8 '18 at 1:29
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    $\begingroup$ Unconditional branch is a category of branches that includes both direct and indirect branches (branch thru register or addressing mode), the latter of which unconditional branches can and are be mispredicted on today's modern hardware. $\endgroup$ – Erik Eidt Feb 8 '18 at 16:48

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