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When an operand encodes an address, and that address changes the "memory address register" and the word in memory being addressed, it seems like timing issues could be a problem. Examples, LDA instruction (load address from memory, load word from that address. )

Illustrated in timing diagram below.

enter image description here

How is this usually solved (could be different across different CPUs but there are probably trends. )

Is a temporary register used (the "memory address register" could load and output in two separate steps), or is the timing issue just not a problem and tends to work out regardless?

Example LDA with two step "memory address register",

      when LDA_1 =>           -- Load accumulator from operand
        addr_in <= dr;
        
        state := LDA_2;
      when LDA_2 =>
        addr_out <= addr_in;
        
        state := LDA_3;
      when LDA_3 =>
        accu <= dr;
        
        state := load_opcode;

Timing with temporary "address in" register illustrated below,

enter image description here

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  • $\begingroup$ I think this is basically the same question as how the program counter can be incremented, right? you're asking how some register value can feed back through some circuits and become the input for its own register? $\endgroup$
    – Criticizing Israel not allowed
    Commented Feb 7, 2023 at 18:13

1 Answer 1

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Well, actually there are many different approaches that can be used, and the optimal solution depends on the specific requirements and constraints of the system.

While using a temporary register, the address is typically loaded into the MAR in a single clock cycle, and then used to access the word in memory in the next clock cycle. This ensures that there is sufficient time for the address to be stable before it is used to access memory.

Well another way is to use a dedicated memory controller, it is responsible for managing the timing of read and write operations to memory. The memory controller can be designed to ensure that the timing constraints of the memory are met, regardless of the speed of the CPU.

These approaches can help ensure that the read operation is successful and the timing constraints of the memory are met. However, as I already said the specific solution will depend on the design of the CPU and the memory system.

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  • $\begingroup$ Thanks for answer. Just relying on data in being ever so dlightly faster than address out, is that any common? Mostly what I want to rule out. Z80 instruction fetch for example seems to read instruction from memory at same rising edge that memory address updates, when I look at their manual, zilog.com/docs/z80/um0080.pdf. $\endgroup$
    – BipedalJoe
    Commented Dec 10, 2022 at 13:17
  • $\begingroup$ @BipedalJoe you mean on PDF page 23 (labeled as page 9)? It shows that the address is stable before /MREQ and /RD go low, and there's most of a clock cycle (at least the high part of the clock cycle) before the CPU reads the values of D7-D0, and the CPU finishes reading before /MREQ or /RD may go high or the address bus may change. At the bottom of page 22/8 it says something similar in words. As the designer of a Z80 computer it's your responsibility to make sure the memory chip's timings and the CPU's timings are compatible, and if not, design some logic to make them compatible. $\endgroup$
    – Criticizing Israel not allowed
    Commented Dec 10, 2022 at 22:39
  • $\begingroup$ What I wondered about mostly was the memory address itself changing while it reads a word in memory (that encodes a new address), if that relies on the very tiny delay that exists inherently and might make it work, or on using intermediary registers and an extra clock cycle. It looks like the Z80 reads the new instruction at the same rising edge as it changes to the next memory address. But I will probably wrap my head around these things eventually. $\endgroup$
    – BipedalJoe
    Commented Dec 11, 2022 at 4:54

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