When the stall is actually going to happen?

Question

Suppose in a 5 stage pipeline when the stall will actually happen if there is a RAW hazard? The stall will start after Instruction Fetch(IF) stage or Instruction decode(ID) stage? In few cases I see that the stall start after IF that is before executing ID and in multicycle pipeline, the stall starts after decode stage (ID). Can someone please clarify it?

Answer 1

As part of the instruction decode phase, the operands are fetched for the instruction. In a very naive pipeline implementation, the operands for read will only be visible after the write instruction has written back its changes to the internal registers (so the last stage).

To prevent such long stalls, a CPU can apply tricks like forwarding the store to the load as soon as the value is determined instead of needing to wait for the write to the registers.

Check out the following for a more detailed answer: https://youtu.be/EL8uqzSsg_Q?t=433

Answer 2

All cpu pipelines are multi-cycle. In the MIPS five-stage pipeline registers are read in the second stage called ID (instruction decode/register fetch). And instructions usually stall as late as possible. For example in

daddi   r1, r2, r3
daddi   r4, r5, r1

the second instruction will stall for three cycles at ID because it can't proceed until the first instruction has written to r1 which happens in the pipeline's fifth stage.