Suppose I have the following MIPS code on a CPU with forwarding enabled:
L1: LW R2 0(R1) ADDI R2 R2 2 SW R2 0(R1) ADDI R1 R1 8 SUB R4 R1 R3 BNEZ R4 L1
The last two lines are of importance for me.
My intuition is that the output to
R4 is calculated during the
EX stage of the pipeline, and should be ready in time for the
BNEZ instruction to
EX in the next cycle. However, I'm getting this output from WinMIPS64:
Why is there a hazard during the
ID stage? Forwarding is enabled, so it ought to know
R4 will be available at the next stage of the pipeline, when it needs to evaluate if
R4 == 0, but it still adds a bubble.
What am I missing here?