There is this problem about pipelining that does not have an answer, and I'm wondering what the answer could be:
In the five stage pipeline with forwarding support to EX, the first operand of ALU comes from 3-to-1 input multiplexer. As the memory latency increases, MEM stage now takes 2 cycles (from 1 cycle) To adjust the pipeline for the latency increase, the MEM stage becomes MEM1 and MEM2.
- How should the input mux for the ALU be changed, if forwarding to EX needs to be fully supported?
- Even with the full forwarding to EX, show an example where the number of stall cycles increase in the new pipeline compared to the old one.
I don't get what it means to divide MEM stage with MEM1 and MEM2. Why would any additional input be necessary?