0
$\begingroup$

There is this problem about pipelining that does not have an answer, and I'm wondering what the answer could be:

enter image description here In the five stage pipeline with forwarding support to EX, the first operand of ALU comes from 3-to-1 input multiplexer. As the memory latency increases, MEM stage now takes 2 cycles (from 1 cycle) To adjust the pipeline for the latency increase, the MEM stage becomes MEM1 and MEM2.

  • How should the input mux for the ALU be changed, if forwarding to EX needs to be fully supported?
  • Even with the full forwarding to EX, show an example where the number of stall cycles increase in the new pipeline compared to the old one.

I don't get what it means to divide MEM stage with MEM1 and MEM2. Why would any additional input be necessary?

$\endgroup$
0
$\begingroup$

This is multi-cycle processor, where each stage takes a single clock cycle. The text suggest that the new MEM stage should take 2 clock cycles. Then, it can be seen as splitting this 2-cycle stage into 2 separate 1-cycle stages which we can call MEM1 and MEM2 respectively.

There is no new input. You only need to make sure that the "right" input travels along the pipeline and reaches the right stage at every time.

$\endgroup$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.