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Use the five-stage pipeline with forwarding unit.

add $t1, $t2, $t3
sw $t1, 0($t4)

In the above code, is the data hazard of t1 fixed by forwarding the correct t1 value from MEM stage to EXE stage?

Also, are there totally four forwarding paths, which are MEMtoEXE, WBtoEXE, MEMtoID, WBtoMEM, in pipeline?

It would be grateful if someone can help. Thank you!

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  • $\begingroup$ Thanks for reminding. I've edited it. $\endgroup$
    – samli50801
    Commented Jan 17, 2023 at 13:57

1 Answer 1

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Here is a pipeline diagram with no bypasses:

enter image description here

The five colors indicate the five stages; fetch (F), decode (D), execute (X), memory (M), and writeback (W). With no bypasses, sw stalls in decode until add has written the value of $t1.

Here is the situation if we assume a bypass from pipeline register X/M to X:

enter image description here

Note that pipeline bypasses are from registers to stages. So it is not technically correct (and slightly confusing) to say that you bypass from, for example, MEMtoEXE because the bypass is actually from M/W to X.

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