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Apparently, each stage of the MIPS processor pipeline takes one CPU cycle. According to this, a memory write can take more than one cycle:

1 cycle to read a register 4 cycles to reach to L1 cache 10 cycles to reach L2 cache 75 cycles to reach L3 cache and hundreds of cycles to reach main memory.

How then can the MEM stage of the MIPS pipeline be said to take 1 cycle?

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    $\begingroup$ The MIPS pipeline (R2000, R3000) assumes two cycle load-to-use (address generation and cache access). The later R4000 pipeline added a second access stage and proceeded to use data before a cache hit was confirmed. The 4 cycle load to use is for a more recent x86 microarchitecture with a pipeline substantially deeper than five or eight stages. $\endgroup$
    – user4577
    Commented Dec 13, 2021 at 12:58

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The MEM stage takes one cycle. But the write isn’t completed at that time. It is completed4, 10, 75 or many cycles later.

If you perform another write instruction, the MEM stage may be stalled until the previous one finishes. Modern processors can queue up many incomplete write instructions. If you perform many write instructions in a row, your processor stalls. If you stop performing write instructions for a while, the incomplete ones will complete.

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  • $\begingroup$ Right, thanks. 1) So the whole "pipelining enables execution of one instruction per cycle" (when the pipeline is full) is only really true if there are writes/reads that get write/read to/from a register (hence facilitating a one cycle read/write)? 2) Can modern processors queue up reads like that can writes? 3) Whilst the reads/writes are being stalled, other instructions can run via Tomasulo's algorithm, right? $\endgroup$
    – Wad
    Commented Dec 12, 2021 at 21:17

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