Difference between memory access and write-back in RISC pipeline

Question

I'm a little confused about the difference of the memory access and the write-back stage in a RISC pipeline.

We learned in class these following assumptions:

arithmetic & logic: IF, OF, EX, WB
load: IF, OF, EX, MA, WB
store: IF, OF, EX, MA
branch: IF, OF, EX

IF=Instruction Fetch, OF=Operand Fetch, EX=Execution, MA=Memory Access, WB=Write-Back

Lets say we have the following code now:

I1: LD R1, 0(R2) ; load R1 from address 0 + R2
I2: ADD R1, R1, #1 ; R1 = R1 + 1
I3: ST 0(R2), R1 ; Store R1 at address 0 + R2

According to what I've learned I1 will pass all five stages, I2 won't have to access the memory, and I3 won't have a write-back.

But then I wonder, how and where does I3 store the value then? Just in the memory? And I2 fetches the value from memory, but needs to write-back to some place other than the memory? So does that mean that write-back is always to the HDD?

I think I'm missing some core concepts here, as to where the operand is fetched from and where it gets stored to.

Answer 1

In a classic 5-stage RISC pipeline, WB writes a value into a register. If the instruction doesn't write a value into a register (e.g. store), then that stage isn't used.

I1 stores a result into a register (namely R1), so it uses WB.

I2 stores a result into a register (R1) so it uses WB.

I3 does not store a result into a register, so it doesn't use WB.

You basically got it with I3: the store instruction stores to memory, so the "write" is performed inside MA.

Incidentally, on "real" RISC machines, MA tends to be more complex (and multi-cycle) because of multi-level caches and virtual memory. A store instruction may cause a page fault, so in a sense it has a "result" that isn't just the memory access.

Answer 2

I did not quite understand your question I am trying to answer.You can ask further if it is not clear.As we know in RISC machine most of the instruction will be performed on registers and memory is addressed only in index mode.I1 will store value in memory address given by R2.I2 will not access memory as it has all sources and destinations as registers.And write back stage is only used for register read and write.

Answer 3

There are also cases a store will have a writeback. For example store-conditional which will return status when accessing a memory location.