PS: MIPS architecture

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This is a model of a memory RAM of 4GB: it has 4,294,967,295 addresses, and each address has 32 bits. Can somebody tell me why the load word instruction needs an offset to the address? My book says that the offset must be multiplied by 4, but for me, I could simply give the address of the array, and then specify which word I wanted to load by saying that the first word is the number 1, the second is the number 2...

So why I need to multiply the offset?


My book says MIPS architecture adresses bytes, not words like I thought. So... wtf? So each address of a memory RAM stores only 8 bits? Does it means that when I access a 32bit address of the RAM via the bus, the RAM outputs just 8 bits data through the same 32 bit BUS? Then,the load word instruction would have to access the RAM 4 times just to transfer the entire word to the register. I don't understand it.

  • $\begingroup$ The offset is used to merge some address computation into the memory access instruction. This is useful for loading a structure member (other than the first) and addressing scalar items in a stack frame or global data area. This delays cache access (which is why Itanium did not support such) but reduces instruction count. $\endgroup$ – Paul A. Clayton Jul 31 '14 at 14:53

Responding only to your UPDATE: MIPS always had load/store byte. The original models may not have allowed unaligned word accesses. Load byte is (relatively) easy on a 32-bit bus. For example, you could fetch the entire word from memory (by setting the bottom 2 address bits to "0") and then add a little circuit so that when the word reaches the processor you use the bottom 2 address bits to shift and mask the correct byte into the destination register.

Store byte is somewhat more complicated. At the beginning of the store-byte operation the processor shifts the byte into the desired position in the 32 bit word, and then sends the entire 32-bit word along with the entire address (including the 2 low-order bits) to the cache. The cache uses the 2 low-order bits to control which bytes do and do-not get written. (The cache has such control (at the word level) anyway, since typically the SRAM array is something like 256x256 bits (= 8Kbytes) or 512x512 bits (= 32Kbytes).)

The only recent architecture I can think of that didn't include load/store byte instructions was the DEC Alpha 21064 (released 1992). Instead they added a lot of special bit shift-and-mask operations to extract bytes from words. If you needed to store a byte on the 21064, I think you may have had to load the word that contained the byte, shifted and masked in the byte that you wanted to write, and then write back the entire word.

They added load/store byte instructions in the 21164A (released 1996) because the extra instructions to do all that extra work in software were making the instruction cache less effective than it should have been for programs with a lot of byte operations.

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  • 2
    $\begingroup$ By the way, the justification (Richard L. Sites, "The Alpha AXP Architecture", Digital Technical Journal, Vol. 4, No. 4, Special Issue, 1992) for lack of load/store byte was the extra delay of more variable shifting for loads and stores and the issue of ECC overhead (5 ECC bits per byte or requiring read-modify-write). $\endgroup$ – Paul A. Clayton Jul 31 '14 at 14:42

If every byte has an address, virtual word adresses ("load the 10th word!") have to be translated into byte addresses ("load the word starting at the 40th byte!"). If you don't do this, you'll load from the middle of the third word (which contains the tenth byte).

You can still load four bytes at once, that is the whole word if the base address was properly chosen. The CPU will just get four bytes starting from the address you give, no questions asked.

Whether you allow for individual bytes to be loaded is mostly a design decision; I think x86 has such instructions but MIPS does not.

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  • $\begingroup$ What happens if I load the word at the address 11 for example? If I load 32(11) shouldn't it be the same as 0(12)? I'm SO confused :'c $\endgroup$ – Revering Sumoda Jul 31 '14 at 20:50

Normally, you would not need to worry about the specific restrictions imposed by the MIPS processor. When defining an array, the compiler perform the multiplication automatically. The compiler/linker would also make sure that the start address of the array is aligned the way the processor need.

However, if you need to understand the details because you are working with the hardware engineer to bring up a new board or you encounter some exceptions related to memory alignment or you just like to know how it work "under the hood", then you may enjoy to read the following.

It is a convention for many processors to define any address in bytes even if every instruction only deal with words.

Let's look at the hardware side relevant to your question. A very common configuration is defined as follow:

data bus (words size): 32 bits

address bus: 30 bits

On the schematic, or when looking directly at the PCB, it can be seen that 32 distinct pins on the CPU are connecting to the RAM for the data bus. As for the address bus, only 30 pins are used. If the processor can connect directly to DRAM, the address bus will actually use only 15 pins, as the bus is multiplexed.

When reading a half word or a byte, the processor actually read all 4 bytes, then it select the appropriate part of the 32 bit value based on the value of A1-A0. We need to remember that the two least significant bits, A1 and A0, do not appear on the actual address bus.

Even if the RAM is using a 32 bit data bus, it allow to write only one byte at a time by using 4 distinct write enable pin. The processor will normally set all 4 write enable to "active" when writing a word. It will set only two of the four write enable when writing a half-word, 16 bits. Finally, only one of the four write enable line will be set to active when writing a byte.

Brief, any 32 bit address inside the processor can effectively appear almost as is on the address bus. More specifically, the 30 most significant bits A31-A2 do appear as is while A1-A0 is kept internally. These 2 bits will determine the value of the 4 write enable signal when writing to RAM.

The multiplication by 4 specified in the MIPS documentation has for effect to uset the 30 most significant bits of the address, A31-A2 while leaving the two least significant bits, A1-A0 to the binary value '00'. In binary, multiplying by 4 is actually shifting the value left by 2 bits.

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