Normally, you would not need to worry about the specific restrictions imposed by the MIPS processor. When defining an array, the compiler perform the multiplication automatically. The compiler/linker would also make sure that the start address of the array is aligned the way the processor need.
However, if you need to understand the details because you are working with the hardware engineer to bring up a new board or you encounter some exceptions related to memory alignment or you just like to know how it work "under the hood", then you may enjoy to read the following.
It is a convention for many processors to define any address in bytes even if every instruction only deal with words.
Let's look at the hardware side relevant to your question. A very common configuration is defined as follow:
data bus (words size): 32 bits
address bus: 30 bits
On the schematic, or when looking directly at the PCB, it can be seen that 32 distinct pins on the CPU are connecting to the RAM for the data bus. As for the address bus, only 30 pins are used. If the processor can connect directly to DRAM, the address bus will actually use only 15 pins, as the bus is multiplexed.
When reading a half word or a byte, the processor actually read all 4 bytes, then it select the appropriate part of the 32 bit value based on the value of A1-A0. We need to remember that the two least significant bits, A1 and A0, do not appear on the actual address bus.
Even if the RAM is using a 32 bit data bus, it allow to write only one byte at a time by using 4 distinct write enable pin. The processor will normally set all 4 write enable to "active" when writing a word. It will set only two of the four write enable when writing a half-word, 16 bits. Finally, only one of the four write enable line will be set to active when writing a byte.
Brief, any 32 bit address inside the processor can effectively appear almost as is on the address bus. More specifically, the 30 most significant bits A31-A2 do appear as is while A1-A0 is kept internally. These 2 bits will determine the value of the 4 write enable signal when writing to RAM.
The multiplication by 4 specified in the MIPS documentation has for effect to uset the 30 most significant bits of the address, A31-A2 while leaving the two least significant bits, A1-A0 to the binary value '00'. In binary, multiplying by 4 is actually shifting the value left by 2 bits.