"In-order" processors only issue instructions in order. Completion is out-of-order even on most processors that are called "in-order". "in-order" just means: if the processor needs to stall the issuing of the next instruction because of a RAW, WAW, or WAR dependence, it can't issue any other instruction during the stall.
If I remember correctly, this is the formula:
Hit time +
(miss rate for cache 1 * (1 - miss rate for cache 2) * miss penalty for cache 1) +
(miss rate for cache 1 * miss rate for cache 2 * miss penalty for cache 2)
Essentially, we just split the case that cache 1 missed into the two cases: cache 2 hit, cache 2 missed.
I believe that if you understand this, ...